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0-In Hosts Verification Tutorial Series at DAC 2004
Leading-Edge Technical Experts to Discuss Methods to Automate
Best Practices for Assertions, Coverage, Verification Hot
Spots and Clock-Domain Crossings
SAN JOSE, Calif.—(BUSINESS WIRE)—May 25, 2004—
0-In Design Automation, the Assertion-Based Verification Company,
will host a series of free one-hour technical mini-tutorials in its
suite (#3243) at the Design Automation Conference (DAC) in San Diego,
June 7 - 11, 2004, to show users how to automate best practices for
using 0-In's assertions, total coverage model, verification hot spots
and complete clock-domain crossing verification to achieve
verification closure faster. Users will be able to learn from and
provide direct feedback to leading edge developers of the most widely
adopted assertion-based and formal verification tools on the market.
The tutorials are a combination of technical presentation and
demonstration on real design examples:
-- "Making the best use of standards-based assertions in design."
-- Presented by Dr. Andrew Seawright
-- "Using the total coverage model to improve the efficiency of
coverage-driven verification."
-- Presented by Dr. Richard Ho
-- "Using exhaustive formal verification to find more bugs in a
simulation-based flow."
-- Presented by Dr. Jeremy Levitt
-- "Complete verification of clock-domain crossings, including
metastability and jitter in digital designs."
-- Presented by Dr. Curt Widdoes
Users will be guided through the technical details of applying
functional verification methodologies to break existing verification
bottlenecks by improving and extending simulation methodologies. The
tutorials are technical in content but assume no advance knowledge of
the subject matters and are aimed at design and verification
engineers, managers and CAD specialists.
Users are invited to register to attend these tutorials at
http://www.0-in.com/dac2004.html.
Archer Verification Automates Best Practices
Also at DAC, 0-In will be highlighting its Archer Verification(TM)
system, which delivers 10x productivity improvements to design and
verification teams working on multi-million gate ASIC and
system-on-chip (SoC) devices. The Archer Verification system automates
tools and provides engineered methodologies built on assertion-based
and formal verification, helping users reach verification closure
through:
-- Assertion automation - which simplifies usage of assertions
with multi-language assertion synthesis and CheckerWare(TM)
library.
-- Total coverage modeling - which includes functional and
structural coverage monitoring and coverage improvement using
formal techniques.
-- Verification hot spots - which automates use of assertions and
formal verification to target the hardest design verification
problems.
Archer Verification's Newest Capabilities to Be Demonstrated
0-In will demonstrate the latest additions to Archer-CDV, which
improves simulation-based, coverage-driven verification by allowing
users to target difficult-to-reach coverage events within their
designs using exhaustive formal analysis. This new capability
identifies the input sequences needed to reach the hardest coverage
events and captures the test as a simulation testbench for users. (See
press release "0-In Boosts Efficiency of Coverage-Driven Verification
with Structural Coverage and Formal Analysis," May 17, 2004.)
0-In also will demonstrate the CDC-FX addition to the Archer
Verification system that provides complete automatic analysis of
clock-domain crossing metastability effects in designs. This
capability allows users to easily detect and fix parts of their design
that are intolerant of variable cycle delays of data and control
signals that cross clock domains. (See press release "0-In Delivers
Automatic Metastability Effects Verification," May 17, 2004.)
More information and on-line registration for product
demonstrations are available at http://www.0-in.com/dac2004.
About the speakers
Dr. Andrew Seawright
Dr. Seawright is a member of the formal verification team at 0-In
and specializes in assertion language synthesis. He has over 10 years
of experience in advanced synthesis techniques and advanced design and
verification methodologies in both EDA and semiconductor companies
including Clearwater Networks, Inc., Chameleon Systems, Inc. and
Synopsys, Inc. Dr. Seawright holds a B.S. in Electrical Engineering
from Rutgers University and M.S. and Ph.D. degrees in Electrical and
Computer Engineering from the University of California at Santa
Barbara.
Dr. Richard Ho
Dr. Ho helped launch the assertion-based verification (ABV)
industry by pioneering the practical applications of formal methods
for functional verification of digital circuits in his Ph.D. thesis
"Validation Tools for Complex Digital Designs." Dr. Ho holds B.Sc. and
M.Eng. degrees in Microelectronic Systems Engineering from the
University of Manchester Institute of Science & Technology (UMIST),
England and a Ph.D. in Computer Science from Stanford University.
Dr. Jeremy Levitt
Dr. Levitt has worked on functional formal verification algorithms
and tools for over 10 years. He was an early member of the 0-In team
and is the lead architect for 0-In formal tools. He holds Ph.D and
M.S. degrees from Stanford University and a B.A.Sc. from the
University of Toronto.
Dr. Curt Widdoes
Dr. Widdoes is widely recognized as a pioneer in the
computer-aided engineering industry. Prior to 0-In, he founded two
successful EDA companies, Logic Modeling Systems Inc. (1987) and Valid
Logic Systems Inc. (1981). Dr. Widdoes holds a B.S. in engineering and
applied science from the California Institute of Technology and a
Ph.D. in computer science from Stanford University. He holds ten
patents and is an IEEE W. Wallace McDowell Award recipient.
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and
supports functional verification products that help verify
multi-million gate application-specific integrated circuit (ASIC) and
system-on-chip (SoC) designs. The company delivers a comprehensive
assertion-based verification (ABV) solution built on industry
standards that provides value throughout the design and verification
cycle - from the block level to the chip and system levels. Twelve of
the 15 largest electronics companies have adopted 0-In tools and
methodologies in their integrated circuit (IC) design verification
flows. 0-In was founded in 1996 and is based in San Jose, Calif. For
more information, see http://www.0-in.com.
0-In(R) and CheckerWare(R) and Archer Verification(TM) are
registered trademarks of 0-In Design Automation, Inc. All other
trademarks are the property of their respective holders.
Contact:
0-In Design Automation
Richard Ho, 408-487-3647
richard@0-in.com
or
Cayenne Communication
(for 0-In Design Automation)
Linda Marchant, 919-683-9545
linda.marchant@cayennecom.com
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